Masked Interrupt Status Register
| RORMIS | This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. |
| RTMIS | This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). |
| RXMIS | This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. |
| TXMIS | This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |